In the current sub-20 nm technology, three dimensional (3D) multi-gate devices (FinFETs or Tri-gates) are primary device structures, which improve gate controllability and suppress current leakage and Short Channel Effects (SCE).
Compared with the conventional single-gate bulk Si or SOI MOSFETs for example, dual-gate SOI structures can suppress the SCE and Drain Induction Barrier Lower (DIBL) effects, have a lower junction capacitance to achieve a lightly-doped channel, and can adjust a threshold voltage by setting a work function of a metal gate to increase a driving current by a factor of about 2, thereby reducing the requirements on Equivalent Oxide Thickness (EOT). Compared with the dual-gate devices, the tri-gate devices have gates surrounding the top surface and opposite sides of the channel, thereby achieving more powerful gate controllability. Further, all-around nanowire multi-gate devices are more advantageous.
In general, a method for manufacturing a FinFET structure comprises: etching in a bulk Si or SOI substrate to form a plurality of Fins and trenches extending in parallel along a first direction; filling the trenches with an insulating material, and implementing etch-back to expose a part of the Fins to form a Shallow Trench Isolation (STI); depositing a thin (merely 1-5 nm, for example) dummy gate insulating layer (generally silicon oxide) on the top and sidewalls of the Fins, and depositing a dummy gate layer (generally polysilicon or amorphous silicon) and a dummy gate blanket layer (generally silicon nitride) on the dummy gate insulating layer; etching the dummy gate layer and the dummy gate insulating layer to form a dummy gate stack extending along a second direction, wherein the second direction is preferably perpendicular to the first direction; implementing a lightly doping implantation process in an inclination angle on the Fins by taking the dummy gate stack as a mask to form a Light Doping Drain (LDD) structure, in particular, a Source Drain Extension (SDE) structure to suppress DIBL effects; depositing and etching at both sides of the dummy gate stack along the first direction to form a gate spacer; epitaxially growing materials with similar lattice constants at both sides of the gate spacer to form source/drain regions with high stress (the gate spacer, the top of the dummy gate stack and the like cannot have a semiconductor material grown epitaxially thereon as they are made of an insulating dielectric material), wherein a material such as SiGe, SiC and the like with higher stress than Si is preferably used to improve carrier mobility; preferably, forming a Contact Etching Stop Layer (CESL) on the source/drain regions; depositing an Inter-Layer Dielectric (ILD) layer on a wafer; etching to remove the dummy gate stack and leave gate trenches in the ILD layer; and depositing, in the gate trenches, a gate insulating layer of a High-k (HK) material, a gate conductive layer of a metal/metal alloy/Metal Nitride (MG), and preferably a gate blanket layer of a nitride material to protect the metal gate. Further, source/drain contact holes are formed by etching the ILD layer using a mask to expose the source/drain regions; and alternatively, metal silicide is formed in the source/drain contact holes to reduce source/drain contact resistances. A contact plug is formed by filling with metal/metal nitride, preferably metal such as W, Ti and the like with a high filling rate. Due to the existence of the CESL and the gate spacer, the filling metal W and Ti will align with the source/drain regions automatically, to finally form the contact plug.
However, although the metal gate and the gate stack structure formed by a high-k material as mentioned above can effectively improve gate controllability, for example, effectively suppress the SCE and accurately adjust a threshold voltage, with the continuous shrinking of the characteristic size (a length of the trench regions, which typically is slightly larger than or equal to a length/width of the metal gate stack along a first direction) of the FinFET device to less than for example 10 nm or even 8 nm, it is difficult to effectively improve the gate trenches formed by a metal material filling gate-last process, and the cost remains at a high level due to the complexity of the process. On the other hand, the conventional polysilicon gate structure which is applied to a planar large-scaled MOSFET is difficult to be applied to the FinFET in a gate-last process, since it is difficult for a device with a short channel and a short gate length to accurately control uniform distribution of the doping agent in the narrow gate, and therefore, the formed polysilicon gate meets technical challenges such as difficulty in control of the SCE, difficulty in accurate adjustment of the threshold voltage and the like.